python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

21 files changed, 36 insertions, 31 deletions

diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index 1bf3b1981..0d76447c8 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from System import System
+
+from m5.objects.System import System
 
 class AlphaSystem(System):
     type = 'AlphaSystem'
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 8031c719f..f2e285360 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index b4e8536a0..70be40313 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -40,8 +40,8 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from ArmPMU import ArmPMU
-from ISACommon import VecRegRenameMode
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ISACommon import VecRegRenameMode
 
 # Enum for DecoderFlavour
 class DecoderFlavour(Enum): vals = ['Generic']
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 3101c33de..53ee04a8b 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+from m5.objects.CPUTracers import NativeTrace
 
 class ArmNativeTrace(NativeTrace):
     type = 'ArmNativeTrace'
diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index cb37ff88c..be9dbb86e 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -42,7 +42,7 @@ from m5.SimObject import *
 from m5.params import *
 from m5.params import isNullPointer
 from m5.proxy import *
-from Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin
 
 class ProbeEvent(object):
     def __init__(self, pmu, _eventId, obj, *listOfNames):
diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 784649914..a804aa8ab 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.SimObject import *
 
-from Serial import SerialDevice
-from Terminal import Terminal
+from m5.objects.Serial import SerialDevice
+from m5.objects.Terminal import Terminal
 
 class ArmSemihosting(SimObject):
     type = 'ArmSemihosting'
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 98ff95918..7ade1e695 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,8 +41,8 @@ from m5.options import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
 
 class ArmMachineType(Enum):
     map = {
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 4cac944f1..c5a8122dd 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
 
 # Basic stage 1 translation objects
 class ArmTableWalker(MemObject):
diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py
index 8955fadd6..7c0e60f59 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -38,7 +38,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class TarmacParser(InstTracer):
     type = 'TarmacParser'
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index 58e30f28d..7a5d8fd76 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -32,7 +32,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from System import System
+from m5.objects.System import System
 
 class MipsSystem(System):
     type = 'MipsSystem'
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index c43cee717..62996ccab 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class MipsTLB(BaseTLB):
     type = 'MipsTLB'
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index b12c5a8e3..5c582b485 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -31,7 +31,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class PowerTLB(BaseTLB):
     type = 'PowerTLB'
diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index 071b211a2..ea1defd90 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -31,8 +31,8 @@
 #          Robert Scheffel
 
 from m5.params import *
-from System import System
 
+from m5.objects.System import System
 
 class RiscvSystem(System):
     type = 'RiscvSystem'
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index bcba00ee0..b24fffb43 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class RiscvTLB(BaseTLB):
     type = 'RiscvTLB'
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index 46b606652..1dbac34c3 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class SparcNativeTrace(NativeTrace):
     type = 'SparcNativeTrace'
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
index 9d8be5d06..60c56c69b 100644
--- a/src/arch/sparc/SparcSystem.py
+++ b/src/arch/sparc/SparcSystem.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 
-from SimpleMemory import SimpleMemory
-from System import System
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.System import System
 
 class SparcSystem(System):
     type = 'SparcSystem'
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 219f6842a..a7bfaea2a 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class SparcTLB(BaseTLB):
     type = 'SparcTLB'
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 5c14679c2..5d4910e98 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -41,7 +41,8 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
 
 class X86LocalApic(BasicPioDevice):
     type = 'X86LocalApic'
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index e6eae8918..798fc879f 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class X86NativeTrace(NativeTrace):
     type = 'X86NativeTrace'
diff --git a/src/arch/x86/X86System.py b/src/arch/x86/X86System.py
index 02185b648..e2ee1b6ec 100644
--- a/src/arch/x86/X86System.py
+++ b/src/arch/x86/X86System.py
@@ -36,11 +36,12 @@
 # Authors: Gabe Black
 
 from m5.params import *
-from E820 import X86E820Table, X86E820Entry
-from SMBios import X86SMBiosSMBiosTable
-from IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
-from ACPI import X86ACPIRSDP
-from System import System
+
+from m5.objects.E820 import X86E820Table, X86E820Entry
+from m5.objects.SMBios import X86SMBiosSMBiosTable
+from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
+from m5.objects.ACPI import X86ACPIRSDP
+from m5.objects.System import System
 
 class X86System(System):
     type = 'X86System'
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 7f195f233..1b2f63d1d 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.proxy import *
 
-from BaseTLB import BaseTLB
-from MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
 
 class X86PagetableWalker(MemObject):
     type = 'X86PagetableWalker'