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| author | Gabor Dozsa <gabor.dozsa@arm.com> | 2018-12-18 15:23:42 +0000 |
|---|---|---|
| committer | Giacomo Gabrielli <giacomo.gabrielli@arm.com> | 2019-07-27 20:51:31 +0000 |
| commit | fc7cb70a7231bb7a92413d1f8b43c9f4ef6c8690 (patch) | |
| tree | 3f28a57a4ac4827a4d6f0969f4b07b13e074d3be /src/arch | |
| parent | 5eb2137d643a373fea2c5828dd6f89002bcb8b0b (diff) | |
| download | gem5-fc7cb70a7231bb7a92413d1f8b43c9f4ef6c8690.tar.xz | |
arch-arm: Fix reg dependency for SVE gather microops
The first microop of an SVE gather creates a copy of the
source vecreg into AA64FpUreg0. The subsequent microops
must refer to this copy as a source in order to establish
the correct register dependencies.
Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/arm/isa/insts/sve_mem.isa | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa index d993122b1..dd3d5827c 100644 --- a/src/arch/arm/isa/insts/sve_mem.isa +++ b/src/arch/arm/isa/insts/sve_mem.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2017-2018 ARM Limited +// Copyright (c) 2017-2019 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -1117,11 +1117,12 @@ let {{ tplHeader = 'template <class RegElemType, class MemElemType>' tplArgs = '<RegElemType, MemElemType>' if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM: - eaCode = ''' + eaCode_store = ''' EA = AA64FpBase_x[elemIndex] + imm * sizeof(MemElemType)''' + eaCode_load = ''' + EA = AA64FpUreg0_x[elemIndex] + imm * sizeof(MemElemType)''' else: - eaCode = ''' - uint64_t offset = AA64FpOffset_x[elemIndex]; + offset_code = ''' if (offsetIs32) { offset &= (1ULL << 32) - 1; } @@ -1132,6 +1133,11 @@ let {{ offset *= sizeof(MemElemType); } EA = XBase + offset''' + eaCode_store = ''' + uint64_t offset = AA64FpOffset_x[elemIndex];''' + offset_code + eaCode_load = ''' + uint64_t offset = AA64FpUreg0_x[elemIndex];''' + offset_code + loadMemAccCode = ''' AA64FpDest_x[elemIndex] = memData; ''' @@ -1149,7 +1155,7 @@ let {{ {'tpl_header': tplHeader, 'tpl_args': tplArgs, 'memacc_code': loadMemAccCode, - 'ea_code' : sveEnabledCheckCode + eaCode, + 'ea_code' : sveEnabledCheckCode + eaCode_load, 'fault_status_set_code' : faultStatusSetCode, 'fault_status_reset_code' : faultStatusResetCode, 'pred_check_code' : predCheckCode, @@ -1163,7 +1169,7 @@ let {{ {'tpl_header': tplHeader, 'tpl_args': tplArgs, 'memacc_code': storeMemAccCode, - 'ea_code' : sveEnabledCheckCode + eaCode, + 'ea_code' : sveEnabledCheckCode + eaCode_store, 'pred_check_code' : predCheckCode, 'fa_code' : ''}, ['IsMicroop', 'IsMemRef', 'IsStore']) |