diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-12 13:09:18 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-23 08:32:25 +0000 |
| commit | 32a23114c14cebc5ec0067ac739144b50e412219 (patch) | |
| tree | 1bc7685956be9cd1b6530c5a07a8232573e9992b /src/base/Graphics.py | |
| parent | e9c7c8168081e38d272e7c83e7f9503b7e8f162f (diff) | |
| download | gem5-32a23114c14cebc5ec0067ac739144b50e412219.tar.xz | |
arch-arm: Trap virtual accesses to GICv3 SGI registers
According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.
Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/base/Graphics.py')
0 files changed, 0 insertions, 0 deletions