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authorAli Saidi <saidi@eecs.umich.edu>2007-03-03 17:22:47 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-03 17:22:47 -0500
commit36f43ff6a5618154f6388650cc2a8526efdd7b30 (patch)
treecfdd7163931c436ed6d04aec815c125e5dedef4d /src/base/bitfield.hh
parentf892608ff7c9898dcbed6dd553632ac2caf4b1ae (diff)
downloadgem5-36f43ff6a5618154f6388650cc2a8526efdd7b30.tar.xz
Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
Diffstat (limited to 'src/base/bitfield.hh')
-rw-r--r--src/base/bitfield.hh25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 0f1233677..83b9138b4 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -112,4 +112,29 @@ replaceBits(T& val, int first, int last, B bit_val)
val = insertBits(val, first, last, bit_val);
}
+/**
+ * Returns the bit position of the MSB that is set in the input
+ */
+inline
+int
+findMsbSet(uint64_t val) {
+ int msb = 0;
+ if (!val)
+ return 0;
+ if (bits(val, 63,32)) msb += 32;
+ val >>= 32;
+ if (bits(val, 31,16)) msb += 16;
+ val >>= 16;
+ if (bits(val, 15,8)) msb += 8;
+ val >>= 8;
+ if (bits(val, 7,4)) msb += 4;
+ val >>= 4;
+ if (bits(val, 3,2)) msb += 2;
+ val >>= 2;
+ if (bits(val, 1,1)) msb += 1;
+ return msb;
+}
+
+
+
#endif // __BASE_BITFIELD_HH__