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authorBoris Shingarov <shingarov@labware.com>2015-12-18 15:12:07 -0600
committerBoris Shingarov <shingarov@labware.com>2015-12-18 15:12:07 -0600
commitd765dbf22cb3242c055b19b797b0f4cb39a43aae (patch)
tree55fade43c664a78e55823cdc43f7bcec1bf663a9 /src/base/remote_gdb.hh
parentb5a54eb64ebce9c217c1d44cc93aebb7cb508c6d (diff)
downloadgem5-d765dbf22cb3242c055b19b797b0f4cb39a43aae.tar.xz
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is modelled using a union of uint8/16/32/64 arrays. The offset positions of each register are expressed as a "register count" scaled according to the width of the register in question. This results in counter- intuitive and error-prone "register count arithmetic", and some formats would even be altogether unrepresentable in such model, e.g. a 64-bit register following a 32-bit one would have a fractional index in the regs64 array. Another difficulty is that the array is allocated before the actual architecture of the workload is known (and therefore before the correct size for the array can be calculated). With this patch I propose a simpler mechanism for expressing the register set structure. In the new code, GdbRegCache is an abstract class; its subclasses contain straightforward structs reflecting the register representation. The determination whether to use e.g. the AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made by polymorphically dispatching getregs() to the concrete subclass. The subclass is not instantiated until it is needed for actual g-/G-packet processing, when the mode is already known. This patch is not meant to be merged in on its own, because it changes the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*, so as it stands right now, it would break the other architectures. In this patch only the base and the ARM code are provided for review; once we agree on the structure, I will provide src/arch/*/remote_gdb.* for the other architectures; those patches could then be merged in together. Review Request: http://reviews.gem5.org/r/3207/ Pushed by Joel Hestness <jthestness@gmail.com>
Diffstat (limited to 'src/base/remote_gdb.hh')
-rw-r--r--src/base/remote_gdb.hh78
1 files changed, 51 insertions, 27 deletions
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index 6cca485e3..2ab7a84dd 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -1,4 +1,5 @@
/*
+ * Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
@@ -27,6 +28,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
+ * Boris Shingarov
*/
#ifndef __REMOTE_GDB_HH__
@@ -99,8 +101,8 @@ class BaseRemoteGDB
//Address formats, break types, and gdb commands may change
//between architectures, so they're defined as virtual
//functions.
- virtual void mem2hex(void *, const void *, int);
- virtual const char * hex2mem(void *, const char *, int);
+ virtual void mem2hex(char *, const char *, int);
+ virtual const char * hex2mem(char *, const char *, int);
virtual const char * break_type(char c);
virtual const char * gdb_command(char cmd);
@@ -150,31 +152,55 @@ class BaseRemoteGDB
ThreadContext *context;
protected:
- class GdbRegCache
+ /**
+ * Concrete subclasses of this abstract class represent how the
+ * register values are transmitted on the wire. Usually each
+ * architecture should define one subclass, but there can be more
+ * if there is more than one possible wire format. For example,
+ * ARM defines both AArch32GdbRegCache and AArch64GdbRegCache.
+ */
+ class BaseGdbRegCache
{
public:
- GdbRegCache(size_t newSize) :
- regs64(new uint64_t[divCeil(newSize, sizeof(uint64_t))]),
- size(newSize)
+
+ /**
+ * Return the pointer to the raw bytes buffer containing the
+ * register values. Each byte of this buffer is literally
+ * encoded as two hex digits in the g or G RSP packet.
+ */
+ virtual char *data() const = 0;
+
+ /**
+ * Return the size of the raw buffer, in bytes
+ * (i.e., half of the number of digits in the g/G packet).
+ */
+ virtual size_t size() const = 0;
+
+ /**
+ * Fill the raw buffer from the registers in the ThreadContext.
+ */
+ virtual void getRegs(ThreadContext*) = 0;
+
+ /**
+ * Set the ThreadContext's registers from the values
+ * in the raw buffer.
+ */
+ virtual void setRegs(ThreadContext*) const = 0;
+
+ /**
+ * Return the name to use in places like DPRINTF.
+ * Having each concrete superclass redefine this member
+ * is useful in situations where the class of the regCache
+ * can change on the fly.
+ */
+ virtual const std::string name() const = 0;
+
+ BaseGdbRegCache(BaseRemoteGDB *g) : gdb(g)
{}
- ~GdbRegCache()
- {
- delete [] regs64;
- }
-
- union {
- uint64_t *regs64;
- uint32_t *regs32;
- uint16_t *regs16;
- uint8_t *regs8;
- void *regs;
- };
- // Size of cache in bytes.
- size_t size;
- size_t bytes() { return size; }
- };
- GdbRegCache gdbregs;
+ protected:
+ BaseRemoteGDB *gdb;
+ };
protected:
uint8_t getbyte();
@@ -192,8 +218,9 @@ class BaseRemoteGDB
template <class T> void write(Addr addr, T data);
public:
- BaseRemoteGDB(System *system, ThreadContext *context, size_t cacheSize);
+ BaseRemoteGDB(System *system, ThreadContext *context);
virtual ~BaseRemoteGDB();
+ virtual BaseGdbRegCache *gdbRegs() = 0;
void replaceThreadContext(ThreadContext *tc) { context = tc; }
@@ -223,9 +250,6 @@ class BaseRemoteGDB
SingleStepEvent singleStepEvent;
- virtual void getregs() = 0;
- virtual void setregs() = 0;
-
void clearSingleStep();
void setSingleStep();