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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-12 13:33:21 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-12 13:33:21 -0400 |
| commit | ba4c224c390916fb489aa7179655c71d7fca1e13 (patch) | |
| tree | 6c02f9acfeb257791c30ad995cc75a0d382e94b8 /src/base/traceflags.py | |
| parent | 78aec04b660544ea7af80d76912b4422c4426602 (diff) | |
| download | gem5-ba4c224c390916fb489aa7179655c71d7fca1e13.tar.xz | |
Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
--HG--
extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
Diffstat (limited to 'src/base/traceflags.py')
| -rw-r--r-- | src/base/traceflags.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py index f871ce35f..c05f9e5b0 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -122,6 +122,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'MemoryAccess', 'O3CPU', 'OzoneCPU', 'OzoneLSQ', |