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| author | Korey Sewell <ksewell@umich.edu> | 2006-07-01 19:02:43 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-07-01 19:02:43 -0400 |
| commit | 23cfd9489bdff00f926f5dcfb7dd72333fb11bfb (patch) | |
| tree | 3f1ac40d6635d76315d3fca9e54309a9a264ce4b /src/base | |
| parent | 62961a291692c960b67158f4152d480c160f8ac8 (diff) | |
| download | gem5-23cfd9489bdff00f926f5dcfb7dd72333fb11bfb.tar.xz | |
traceflag stuff
src/base/traceflags.py:
add BaseCPU flag, O3CPUAll flag grouping
src/cpu/base.cc:
Use BaseCPU flag instead of FullCPU flag
--HG--
extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179
Diffstat (limited to 'src/base')
| -rw-r--r-- | src/base/traceflags.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py index c4dcb695b..d51236c46 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -115,6 +115,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'BaseCPU' 'O3CPU', 'OzoneCPU', 'FE', @@ -176,7 +177,7 @@ compoundFlagMap = { 'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ], 'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ], - 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'], + 'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity','Scoreboard','Writeback'], 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU'] } |