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authorAli Saidi <saidi@eecs.umich.edu>2006-12-06 14:29:10 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-12-06 14:29:10 -0500
commitecbb8debf672ee1463115319a24384eeb6b98ee3 (patch)
treedc42fa3886ff50fd9786858987e9cbd6c7b23f1b /src/base
parent4d57cab49a3012e812a054517317e95734ea8678 (diff)
downloadgem5-ecbb8debf672ee1463115319a24384eeb6b98ee3.tar.xz
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
Diffstat (limited to 'src/base')
-rw-r--r--src/base/traceflags.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 92735aa5f..c06399f81 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -109,6 +109,7 @@ baseFlags = [
'IIC',
'IICMore',
'IPI',
+ 'IPR',
'IQ',
'ISP',
'IdeCtrl',