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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 22:50:36 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-10 22:50:36 -0400 |
| commit | 1de8eae43a5310ff6e6b76ef0554c08800ac01ed (patch) | |
| tree | 5608f789e75fc4c6baa47e59923f662a65c796f2 /src/base | |
| parent | 27c59dc370f2f851a8426d6024fa4d2acb296238 (diff) | |
| download | gem5-1de8eae43a5310ff6e6b76ef0554c08800ac01ed.tar.xz | |
Debugging info
src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
--HG--
extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
Diffstat (limited to 'src/base')
| -rw-r--r-- | src/base/traceflags.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 274407be5..f871ce35f 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -58,6 +58,7 @@ baseFlags = [ 'BusAddrRanges', 'BusBridge', 'Cache', + 'CachePort', 'Chains', 'Checker', 'Clock', |