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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-05 15:13:27 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-05 15:13:27 -0400 |
| commit | 4201ec84b2dd7d96148bf661124dd7b5d0e7204b (patch) | |
| tree | 1886edde38b2da28cb45f4e13135b1993502f45d /src/base | |
| parent | f4c5609988731f52f9c5bd84ee2db364bbf6fd97 (diff) | |
| download | gem5-4201ec84b2dd7d96148bf661124dd7b5d0e7204b.tar.xz | |
Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function.
src/cpu/simple/timing.cc:
Set the thread context in the CPU.
Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
Properly implement the allocate function for the MSHR.
--HG--
extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
Diffstat (limited to 'src/base')
0 files changed, 0 insertions, 0 deletions