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authorLisa Hsu <hsul@eecs.umich.edu>2006-12-08 14:37:31 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2006-12-08 14:37:31 -0500
commitda6c1f5b096288f13bd4c608b40d1caa84c4de49 (patch)
tree2df4e6a0bfdc95d257977d826ada26870f710057 /src/base
parent03be92f23b36ba69bfee179f97cd5af23c0f6e2c (diff)
downloadgem5-da6c1f5b096288f13bd4c608b40d1caa84c4de49.tar.xz
mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh: add in thread_context.hh to get access to tc. get rid of stubs that don't make sense right now. implement checking and get softint interrupts src/arch/sparc/miscregfile.cc: softint should be OR-ed on a write. src/arch/sparc/miscregfile.hh: add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs. src/arch/sparc/ua2005.cc: implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write. --HG-- extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
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