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authorFernando Endo <fernando.endo2@gmail.com>2016-10-15 14:58:45 -0500
committerFernando Endo <fernando.endo2@gmail.com>2016-10-15 14:58:45 -0500
commit6c72c3551978ef2eabbe9727bf24fd2fcf385318 (patch)
treed7b37cfe5b12e2136afe5f90ea22d67a512d0018 /src/base
parent2f5262eb67f0539ab6c07d56eeae1b72f6b6b509 (diff)
downloadgem5-6c72c3551978ef2eabbe9727bf24fd2fcf385318.tar.xz
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which distinguishes writes to the INT and FP register banks. Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72, where the "latency" of FMADD is 3 if the next instruction is a FMADD and has only the augend to destination dependency, otherwise it's 7 cycles. Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
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