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| author | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2007-08-12 09:56:37 -0700 |
| commit | 64295b800fd67e9b9bb3eee0131511a71ddf1fdb (patch) | |
| tree | ed1c759f11384dd2c263b43d7842be2922c5c39d /src/cpu/BaseCPU.py | |
| parent | b92594dd90f54a892771989a8164148e6647c9ab (diff) | |
| parent | ec4000e0e284834df0eb1db792074a1b11f21cc8 (diff) | |
| download | gem5-64295b800fd67e9b9bb3eee0131511a71ddf1fdb.tar.xz | |
merge
--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 8be84392d..7a51650e6 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -93,10 +93,11 @@ class BaseCPU(SimObject): def connectMemPorts(self, bus): for p in self._mem_ports: - exec('self.%s = bus.port' % p) + if p != 'physmem_port': + exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2) + assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side |