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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:22 -0800 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-12-01 00:15:22 -0800 |
| commit | 946f7f0f55215d0eefe29fed2e4c123e23b9848f (patch) | |
| tree | 312ff2a3a263cd79e700c8ef3e6a85ddd5ff8884 /src/cpu/BaseCPU.py | |
| parent | 5901c5223f2e9280aa6f2307288b6a5dc554df83 (diff) | |
| download | gem5-946f7f0f55215d0eefe29fed2e4c123e23b9848f.tar.xz | |
ARM: Add support for having a TLB cache.
--HG--
extra : rebase_source : 7a5780ab74d7c294682738c7ccb3ce8d56c6fd63
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index bf7577cc7..665d42af0 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -182,15 +182,16 @@ class BaseCPU(MemObject): self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] if buildEnv['FULL_SYSTEM']: - if buildEnv['TARGET_ISA'] == 'x86': - self.itb_walker_cache = iwc - self.dtb_walker_cache = dwc - self.itb.walker.port = iwc.cpu_side - self.dtb.walker.port = dwc.cpu_side - self._cached_ports += ["itb_walker_cache.mem_side", \ - "dtb_walker_cache.mem_side"] - elif buildEnv['TARGET_ISA'] == 'arm': - self._cached_ports += ["itb.walker.port", "dtb.walker.port"] + if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if iwc and dwc: + self.itb_walker_cache = iwc + self.dtb_walker_cache = dwc + self.itb.walker.port = iwc.cpu_side + self.dtb.walker.port = dwc.cpu_side + self._cached_ports += ["itb_walker_cache.mem_side", \ + "dtb_walker_cache.mem_side"] + else: + self._cached_ports += ["itb.walker.port", "dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |