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| author | Gabe Black <gabeblack@google.com> | 2018-03-05 22:05:47 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-03-06 23:39:01 +0000 |
| commit | 0bb50e6745b35c785c4d8051eb43f6bc419fb924 (patch) | |
| tree | 97dfd086d6e4b3f4252aec459091ff6dad19f2b6 /src/cpu/BaseCPU.py | |
| parent | 10e5646dbbe46aa317ec568cb2a58968ca867575 (diff) | |
| download | gem5-0bb50e6745b35c785c4d8051eb43f6bc419fb924.tar.xz | |
scons: Switch from the print statement to the print function.
Starting with version 3, scons imposes using the print function instead
of the print statement in code it processes. To get things building
again, this change moves all python code within gem5 to use the
function version. Another change by another author separately made this
same change to the site_tools and site_init.py files.
Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0
Reviewed-on: https://gem5-review.googlesource.com/8761
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 096aa635e..e02d36724 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -42,6 +42,8 @@ # Andreas Hansson # Glenn Bergmans +from __future__ import print_function + import sys from m5.SimObject import * @@ -200,8 +202,8 @@ class BaseCPU(MemObject): [], "Interrupt Controller") isa = VectorParam.RiscvISA([], "ISA instance") else: - print "Don't know what TLB to use for ISA %s" % \ - buildEnv['TARGET_ISA'] + print("Don't know what TLB to use for ISA %s" % + buildEnv['TARGET_ISA']) sys.exit(1) max_insts_all_threads = Param.Counter(0, @@ -260,8 +262,8 @@ class BaseCPU(MemObject): self.interrupts = \ [RiscvInterrupts() for i in xrange(self.numThreads)] else: - print "Don't know what Interrupt Controller to use for ISA %s" % \ - buildEnv['TARGET_ISA'] + print("Don't know what Interrupt Controller to use for ISA %s" % + buildEnv['TARGET_ISA']) sys.exit(1) def connectCachedPorts(self, bus): |