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| author | Akash Bagdia <akash.bagdia@arm.com> | 2014-05-09 18:58:46 -0400 |
|---|---|---|
| committer | Akash Bagdia <akash.bagdia@arm.com> | 2014-05-09 18:58:46 -0400 |
| commit | 2b1a01ee6ccda9f046b1ceb13c90ee0635473959 (patch) | |
| tree | 1877032b428dce5a8cbfd69f0f974b1015184a0d /src/cpu/BaseCPU.py | |
| parent | e940bac278a877699238f9c70748762ea9379db4 (diff) | |
| download | gem5-2b1a01ee6ccda9f046b1ceb13c90ee0635473959.tar.xz | |
cpu, arm: Allow the specification of a socket field
Allow the specification of a socket ID for every core that is reflected in the
MPIDR field in ARM systems. This allows studying multi-socket / cluster
systems with ARM CPUs.
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 652af0b80..b7f0b2089 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -128,6 +128,7 @@ class BaseCPU(MemObject): system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") + socket_id = Param.Unsigned(0, "Physical Socket identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") function_trace = Param.Bool(False, "Enable function trace") |