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authorNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) <nilay@cs.wisc.edu>2013-01-24 12:28:51 -0600
committerNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) <nilay@cs.wisc.edu>2013-01-24 12:28:51 -0600
commitdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (patch)
tree568d3b6007adf1a8d3ba6568fc5635e56afd3d53 /src/cpu/BaseCPU.py
parent11d5ffa108983d5d9742f0aad23f80c691f285ee (diff)
downloadgem5-dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f.tar.xz
branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. --HG-- rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r--src/cpu/BaseCPU.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 900a23991..759bc0881 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -51,6 +51,7 @@ from Bus import CoherentBus
from InstTracer import InstTracer
from ExeTracer import ExeTracer
from MemObject import MemObject
+from BranchPredictor import BranchPredictor
default_tracer = ExeTracer()
@@ -184,6 +185,8 @@ class BaseCPU(MemObject):
dcache_port = MasterPort("Data Port")
_cached_ports = ['icache_port', 'dcache_port']
+ branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
+
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
_cached_ports += ["itb.walker.port", "dtb.walker.port"]