cpu: Flush TLBs on switchOut()

This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching. Additionally, the
TLB flushing functionality is exported to the Python to make debugging
of switching/checkpointing easier.

A simulation script will typically use the TLB flushing functionality
to generate a reference trace. The following sequence can be used to
simulate a handover (this depends on how drain is implemented, but is
generally the case) between identically configured CPU models:

  m5.drain(test_sys)
  [ cpu.flushTLBs() for cpu in test_sys.cpu ]
  m5.resume(test_sys)

The generated trace should normally be identical to a trace generated
when switching between identically configured CPU models or
checkpointing and resuming.

1 files changed, 1 insertions, 0 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6673b9d41..900a23991 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -96,6 +96,7 @@ class BaseCPU(MemObject):
     void switchOut();
     void takeOverFrom(BaseCPU *cpu);
     bool switchedOut();
+    void flushTLBs();
 ''')
 
     def takeOverFrom(self, old_cpu):