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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-31 22:40:08 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-31 22:40:08 -0800 |
| commit | ea8b347dc5d375572d8d19770024ec8be5fd5017 (patch) | |
| tree | 56bb75b1f071a749b7e90218d0d6b0e9265657bb /src/cpu/BaseCPU.py | |
| parent | e88165a431a90cf7e33e205794caed898ca6fcb1 (diff) | |
| parent | 7d4f18770073d968c70cd3ffcdd117f50a6056a2 (diff) | |
| download | gem5-ea8b347dc5d375572d8d19770024ec8be5fd5017.tar.xz | |
Merge with head, hopefully the last time for this batch.
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 19464acbc..fda0a3bc8 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -164,7 +164,6 @@ class BaseCPU(MemObject): self.connectUncachedPorts(uncached_bus) def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): - assert(len(self._cached_ports) < 7) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side @@ -180,6 +179,11 @@ class BaseCPU(MemObject): "dtb_walker_cache.mem_side"] else: self._cached_ports += ["itb.walker.port", "dtb.walker.port"] + # Checker doesn't need its own tlb caches because it does + # functional accesses only + if buildEnv['USE_CHECKER']: + self._cached_ports += ["checker.itb.walker.port", \ + "checker.dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |