diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:15:35 -0800 |
| commit | ec936364b7238cddea7734ea79c6e04b52a683c6 (patch) | |
| tree | 788fc19c3ba599d6f39d3990769888a0650be5ff /src/cpu/BaseCPU.py | |
| parent | 36a822f08e88483b41af214ace4fd3dccf3aa8cb (diff) | |
| parent | 9b52717a92ed9592bd98a41683509f538262a5c7 (diff) | |
| download | gem5-ec936364b7238cddea7734ea79c6e04b52a683c6.tar.xz | |
Merge with the main repository again.
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index b5c203742..50a8501e2 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -167,15 +167,16 @@ class BaseCPU(MemObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] - if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc: - self.itb_walker_cache = iwc - self.dtb_walker_cache = dwc - self.itb.walker.port = iwc.cpu_side - self.dtb.walker.port = dwc.cpu_side - self._cached_ports += ["itb_walker_cache.mem_side", \ - "dtb_walker_cache.mem_side"] - elif buildEnv['TARGET_ISA'] == 'arm': - self._cached_ports += ["itb.walker.port", "dtb.walker.port"] + if buildEnv['TARGET_ISA'] in ['x86', 'arm']: + if iwc and dwc: + self.itb_walker_cache = iwc + self.dtb_walker_cache = dwc + self.itb.walker.port = iwc.cpu_side + self.dtb.walker.port = dwc.cpu_side + self._cached_ports += ["itb_walker_cache.mem_side", \ + "dtb_walker_cache.mem_side"] + else: + self._cached_ports += ["itb.walker.port", "dtb.walker.port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) |