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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 13:28:54 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 13:28:54 -0700
commit557bde43c331024eb5cecf4093a24a5b7a9cc266 (patch)
treeb5bf7d105deb94b19098c431263aa6304bcae333 /src/cpu/BaseCPU.py
parente4590131825d27293d9642d2ac118ff03cc894f4 (diff)
downloadgem5-557bde43c331024eb5cecf4093a24a5b7a9cc266.tar.xz
X86: Make APICs communicate through the memory system.
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r--src/cpu/BaseCPU.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 78b9ae944..51d447f0b 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -144,7 +144,8 @@ class BaseCPU(MemObject):
if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
_mem_ports = ["itb.walker.port",
"dtb.walker.port",
- "interrupts.pio"]
+ "interrupts.pio",
+ "interrupts.int_port"]
def connectMemPorts(self, bus):
for p in self._mem_ports: