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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 18:06:57 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 18:06:57 -0800 |
| commit | 1048b548fabfb7af2113f226f2151d3eb0e63289 (patch) | |
| tree | d68b47ad4f335ade253f5ae87a158c6209d6ec20 /src/cpu/BaseCPU.py | |
| parent | 6095dceb0c34cf79ecbd799ab4b2cbe7b7c8629a (diff) | |
| download | gem5-1048b548fabfb7af2113f226f2151d3eb0e63289.tar.xz | |
X86: Separate out the page table walker into it's own cc and hh.
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index cb5793e57..9fc1db9f1 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -101,9 +101,7 @@ class BaseCPU(SimObject): _mem_ports = [] if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - itb.walker_port = Port("ITB page table walker port") - dtb.walker_port = Port("ITB page table walker port") - _mem_ports = ["itb.walker_port", "dtb.walker_port"] + _mem_ports = ["itb.walker.port", "dtb.walker.port"] def connectMemPorts(self, bus): for p in self._mem_ports: |