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author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-28 20:30:43 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-28 20:30:43 -0700 |
commit | 8dd7700482b8ad7fa5e96469b23f0c917f5e3599 (patch) | |
tree | c1e9e7e835a12992eda9f9ee90e4f984816ed059 /src/cpu/BaseCPU.py | |
parent | cda354b07035f73a3b220f89014721300d36a815 (diff) | |
download | gem5-8dd7700482b8ad7fa5e96469b23f0c917f5e3599.tar.xz |
Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.
--HG--
extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r-- | src/cpu/BaseCPU.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6c2aace51..8be84392d 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -31,8 +31,12 @@ from m5.params import * from m5.proxy import * from m5 import build_env from Bus import Bus +from InstTracer import InstTracer +from ExeTracer import ExeTracer import sys +default_tracer = ExeTracer() + if build_env['FULL_SYSTEM']: if build_env['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB @@ -83,6 +87,8 @@ class BaseCPU(SimObject): clock = Param.Clock('1t', "clock speed") phase = Param.Latency('0ns', "clock phase") + tracer = Param.InstTracer(default_tracer, "Instruction tracer") + _mem_ports = [] def connectMemPorts(self, bus): |