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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353 (patch) | |
| tree | 14b4f11266600c44ec4c1846665277115911b363 /src/cpu/BaseCPU.py | |
| parent | 1c8dfd92543aba5f49e464b17e7e8143fc01a58c (diff) | |
| download | gem5-b569f8f0ed8dcf32347f0d4f68d2d7572a5d1353.tar.xz | |
inorder-bpred: edits to handle non-delay-slot ISAs
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
Diffstat (limited to 'src/cpu/BaseCPU.py')
0 files changed, 0 insertions, 0 deletions