diff options
author | Nathan Binkert <nate@binkert.org> | 2008-08-11 12:22:16 -0700 |
---|---|---|
committer | Nathan Binkert <nate@binkert.org> | 2008-08-11 12:22:16 -0700 |
commit | ee62a0fec8e63f45f816c61ab9fb28aba7414185 (patch) | |
tree | a66f43493f7d7eacbd2ee0d3351bab6a50639447 /src/cpu/BaseCPU.py | |
parent | 3448a122085797a902e776f47bfe69a078bfca5e (diff) | |
download | gem5-ee62a0fec8e63f45f816c61ab9fb28aba7414185.tar.xz |
params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r-- | src/cpu/BaseCPU.py | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c2a865113..1e3f0dbbc 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -26,7 +26,7 @@ # # Authors: Nathan Binkert -from m5.SimObject import SimObject +from MemObject import MemObject from m5.params import * from m5.proxy import * from m5 import build_env @@ -48,14 +48,21 @@ elif build_env['TARGET_ISA'] == 'mips': elif build_env['TARGET_ISA'] == 'arm': from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB -class BaseCPU(SimObject): +class BaseCPU(MemObject): type = 'BaseCPU' abstract = True system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") + numThreads = Param.Unsigned(1, "number of HW thread contexts") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + + checker = Param.BaseCPU("checker CPU") if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") do_quiesce = Param.Bool(True, "enable quiesce instructions") do_checkpoint_insts = Param.Bool(True, "enable checkpoint pseudo instructions") |