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| author | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
|---|---|---|
| committer | Vincentius Robby <acolyte@umich.edu> | 2007-08-08 18:43:12 -0400 |
| commit | ec4000e0e284834df0eb1db792074a1b11f21cc8 (patch) | |
| tree | 9b42b9697c8fe3cf00c3ab8257002146d8d37a9c /src/cpu/BaseCPU.py | |
| parent | 1caed1465470269c36897904edddf8d4dc9765b1 (diff) | |
| download | gem5-ec4000e0e284834df0eb1db792074a1b11f21cc8.tar.xz | |
Added fastmem option.
Lets CPU accesses to physical memory bypass Bus.
--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 8be84392d..7a51650e6 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -93,10 +93,11 @@ class BaseCPU(SimObject): def connectMemPorts(self, bus): for p in self._mem_ports: - exec('self.%s = bus.port' % p) + if p != 'physmem_port': + exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2) + assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side |