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author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
commit | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (patch) | |
tree | a736f3746d5c38bdc98d6fb8589113556271d486 /src/cpu/BaseCPU.py | |
parent | 69d419f31383ac7801e1debb62d5bbf7cb899e3c (diff) | |
download | gem5-3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98.tar.xz |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r-- | src/cpu/BaseCPU.py | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index dfbd459fd..697be87e1 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -57,21 +57,33 @@ default_tracer = ExeTracer() if buildEnv['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB from AlphaInterrupts import AlphaInterrupts + from AlphaISA import AlphaISA + isa_class = AlphaISA elif buildEnv['TARGET_ISA'] == 'sparc': from SparcTLB import SparcTLB from SparcInterrupts import SparcInterrupts + from SparcISA import SparcISA + isa_class = SparcISA elif buildEnv['TARGET_ISA'] == 'x86': from X86TLB import X86TLB from X86LocalApic import X86LocalApic + from X86ISA import X86ISA + isa_class = X86ISA elif buildEnv['TARGET_ISA'] == 'mips': from MipsTLB import MipsTLB from MipsInterrupts import MipsInterrupts + from MipsISA import MipsISA + isa_class = MipsISA elif buildEnv['TARGET_ISA'] == 'arm': from ArmTLB import ArmTLB from ArmInterrupts import ArmInterrupts + from ArmISA import ArmISA + isa_class = ArmISA elif buildEnv['TARGET_ISA'] == 'power': from PowerTLB import PowerTLB from PowerInterrupts import PowerInterrupts + from PowerISA import PowerISA + isa_class = PowerISA class BaseCPU(MemObject): type = 'BaseCPU' @@ -113,31 +125,37 @@ class BaseCPU(MemObject): itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") interrupts = Param.SparcInterrupts( NULL, "Interrupt Controller") + isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") interrupts = Param.AlphaInterrupts( NULL, "Interrupt Controller") + isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") interrupts = Param.X86LocalApic(NULL, "Interrupt Controller") + isa = VectorParam.X86ISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") interrupts = Param.MipsInterrupts( NULL, "Interrupt Controller") + isa = VectorParam.MipsISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") interrupts = Param.ArmInterrupts( NULL, "Interrupt Controller") + isa = VectorParam.ArmISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") interrupts = Param.PowerInterrupts( NULL, "Interrupt Controller") + isa = VectorParam.PowerISA([ isa_class() ], "ISA instance") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] @@ -241,5 +259,10 @@ class BaseCPU(MemObject): self.toL2Bus.master = self.l2cache.cpu_side self._cached_ports = ['l2cache.mem_side'] + def createThreads(self): + self.isa = [ isa_class() for i in xrange(self.numThreads) ] + if self.checker != NULL: + self.checker.createThreads() + def addCheckerCpu(self): pass |