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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-29 13:25:14 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-29 13:25:14 -0700 |
| commit | 08474ccf68e14f59b4517c6024a9bc6ecbd4a1d5 (patch) | |
| tree | 5c1dc885b4fd33fc48d91a9ce489e24c88c9f3c2 /src/cpu/BaseCPU.py | |
| parent | 4a7d0c4b79450e05b87da4cfc48c2361758127c1 (diff) | |
| parent | 362ff1bcebd78c0c247e435eac657c8a1134b1fb (diff) | |
| download | gem5-08474ccf68e14f59b4517c6024a9bc6ecbd4a1d5.tar.xz | |
Merge Gabe's changes from head.
--HG--
extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6c2aace51..8be84392d 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -31,8 +31,12 @@ from m5.params import * from m5.proxy import * from m5 import build_env from Bus import Bus +from InstTracer import InstTracer +from ExeTracer import ExeTracer import sys +default_tracer = ExeTracer() + if build_env['FULL_SYSTEM']: if build_env['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB @@ -83,6 +87,8 @@ class BaseCPU(SimObject): clock = Param.Clock('1t', "clock speed") phase = Param.Latency('0ns', "clock phase") + tracer = Param.InstTracer(default_tracer, "Instruction tracer") + _mem_ports = [] def connectMemPorts(self, bus): |