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author | Gabe Black <gabeblack@google.com> | 2019-08-08 15:28:18 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2019-08-10 03:50:16 +0000 |
commit | 386e2018fa81a467d0fafc9882290a17032fb891 (patch) | |
tree | 486706fdeb112d8294e2df5bde3387734c7a987c /src/cpu/BaseCPU.py | |
parent | c9e0a5f200a023b0687428561fbcefc9332f93c2 (diff) | |
download | gem5-386e2018fa81a467d0fafc9882290a17032fb891.tar.xz |
x86: Move some fixed or dummy config information into X86LocalApic.py.
The X86 local APIC doesn't actually use the pio_addr set in the config
and instead computes what address it will respond to based on the
initial ID of the CPU it's attached to. gem5's BasicPioDevice, which
the X86LocalApic class inherits from, does not provide a default value
for that parameter and will complain if *something* isn't set. The
value used, 0x2000000000000000, is a dummy value which is the base of
the region of the physical address space set aside for messages to
local APICs from the CPU and from other local APICs.
Also, the clock for the local APIC's timer is defined to be the bus
clock. The assumption seems to be that this has a 16:1 ratio with the
CPU clock, and I vaguely remember finding that that was more or less
unofficially true, even if it isn't necessary stringently defined to
be that.
Since we were already just assuming that that ratio was correct and
always setting up the local APICs clock that way, we can do that in
the X86LocalApic class definition and remove some special x86 specific
setup that we'd otherwise need for the x86 version of the Interrupt
class. If that's not correct, it can still be overridden somewhere else
in the config.
Change-Id: I50e84f899f44b1191c2ad79d05803b44f07001f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19968
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu/BaseCPU.py')
-rw-r--r-- | src/cpu/BaseCPU.py | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 6dd460cbe..2486c2e67 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -245,13 +245,7 @@ class BaseCPU(ClockedObject): elif buildEnv['TARGET_ISA'] == 'alpha': self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'x86': - self.apic_clk_domain = DerivedClockDomain(clk_domain = - Parent.clk_domain, - clk_divider = 16) - self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain, - pio_addr=0x2000000000000000) - for i in range(self.numThreads)] - _localApic = self.interrupts + self.interrupts = [X86LocalApic() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'mips': self.interrupts = [MipsInterrupts() for i in range(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'arm': |