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| author | Gabe Black <gabeblack@google.com> | 2019-09-11 16:45:41 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-18 21:50:26 +0000 |
| commit | c75d185d8ada4345ac3323b6603fedc4a79c94cc (patch) | |
| tree | 5ad202d1fd8ffad1d46563076ca03e49225e46c1 /src/cpu/BaseCPU.py | |
| parent | cb1d9d5774b04d6acb6fc3cf27f2bab870f69fc2 (diff) | |
| download | gem5-c75d185d8ada4345ac3323b6603fedc4a79c94cc.tar.xz | |
x86: Turn the local APIC Interrupts class into a SimObject.
It will no longer be a PioDevice or a ClockedObject, but will carry
forward the little bits and pieces of those classes that it was using.
Those are a PIO port for memory mapped register accesses, and a clock
domain parameter for setting the apic tick frequency.
This brings the x86 Interrupts class in line with the Interrupts of the
other ISAs so that they can inherit from a standard base class.
Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu/BaseCPU.py')
0 files changed, 0 insertions, 0 deletions