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| author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
| commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
| tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/cpu/BaseCPU.py | |
| parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
| download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz | |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/cpu/BaseCPU.py')
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 93cb6e071..6dd460cbe 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -52,10 +52,10 @@ from m5.params import * from m5.proxy import * from m5.util.fdthelper import * +from m5.objects.ClockedObject import ClockedObject from m5.objects.XBar import L2XBar from m5.objects.InstTracer import InstTracer from m5.objects.CPUTracers import ExeTracer -from m5.objects.MemObject import MemObject from m5.objects.SubSystem import SubSystem from m5.objects.ClockDomain import * from m5.objects.Platform import Platform @@ -99,7 +99,7 @@ elif buildEnv['TARGET_ISA'] == 'riscv': from m5.objects.RiscvISA import RiscvISA default_isa_class = RiscvISA -class BaseCPU(MemObject): +class BaseCPU(ClockedObject): type = 'BaseCPU' abstract = True cxx_header = "cpu/base.hh" |