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author | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:17 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:17 -0500 |
commit | 0bd986015b2de741dc741f10e5afeaf5d8890ba1 (patch) | |
tree | b264b3fd434124d7b04eb4a6b337cb38e8ccb305 /src/cpu/CPUTracers.py | |
parent | 6c4a23c1c637d77f60df9516d0f36c71d12a2298 (diff) | |
download | gem5-0bd986015b2de741dc741f10e5afeaf5d8890ba1.tar.xz |
cpu: Put all CPU instruction tracers in a single file
Diffstat (limited to 'src/cpu/CPUTracers.py')
-rw-r--r-- | src/cpu/CPUTracers.py | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py new file mode 100644 index 000000000..df7a8939f --- /dev/null +++ b/src/cpu/CPUTracers.py @@ -0,0 +1,48 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.SimObject import SimObject +from m5.params import * +from InstTracer import InstTracer + +class ExeTracer(InstTracer): + type = 'ExeTracer' + cxx_class = 'Trace::ExeTracer' + cxx_header = "cpu/exetrace.hh" + +class IntelTrace(InstTracer): + type = 'IntelTrace' + cxx_class = 'Trace::IntelTrace' + cxx_header = "cpu/inteltrace.hh" + +class NativeTrace(ExeTracer): + abstract = True + type = 'NativeTrace' + cxx_class = 'Trace::NativeTrace' + cxx_header = 'cpu/nativetrace.hh' + |