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authorMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
commitccf4f6c3d7616c546d78eb21d22ebda812b5e2bb (patch)
tree08581c6baa40737335733f39d4bab87611ddccee /src/cpu/CheckerCPU.py
parent9e07a7504c94973e7837d1d3e96dbdb8d95cfad3 (diff)
downloadgem5-ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb.tar.xz
arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is detected. Having 2 SMT threads share a TLB resulted in these not being updated as required. This patch adds a thread context identifer to assist in the invalidation of these variables.
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