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| author | Gabe Black <gabeblack@google.com> | 2014-12-05 01:44:24 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2014-12-05 01:44:24 -0800 |
| commit | fe48c0a32bf749358eeb95e748f9fc2247cc5480 (patch) | |
| tree | 25e64817703c264bf09fa884db7eb187927870f7 /src/cpu/FuncUnit.py | |
| parent | 7540656fc5b8ce0cafb54f41b913a7e81cbfb4b3 (diff) | |
| download | gem5-fe48c0a32bf749358eeb95e748f9fc2247cc5480.tar.xz | |
misc: Make the GDB register cache accessible in various sized chunks.
Not all ISAs have 64 bit sized registers, so it's not always very convenient
to access the GDB register cache in 64 bit sized chunks. This change makes it
accessible in 8, 16, 32, or 64 bit chunks. The MIPS and ARM implementations
were working around that limitation by bundling and unbundling 32 bit values
into 64 bit values. That code has been removed.
Diffstat (limited to 'src/cpu/FuncUnit.py')
0 files changed, 0 insertions, 0 deletions