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authorAli Saidi <Ali.Saidi@ARM.com>2015-02-16 03:32:38 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2015-02-16 03:32:38 -0500
commit4eff4fa12eafbf6337fdf9a23668880ad55aad9c (patch)
tree7ea64da7b8684c00ba127ffbe8ccca5d0cbeebff /src/cpu/InstPBTrace.py
parent268d9e59c5e69a00456a40c837b0150a8f3f6bf8 (diff)
downloadgem5-4eff4fa12eafbf6337fdf9a23668880ad55aad9c.tar.xz
cpu: add support for outputing a protobuf formatted CPU trace
Doesn't support x86 due to static instruction representation. --HG-- rename : src/cpu/CPUTracers.py => src/cpu/InstPBTrace.py
Diffstat (limited to 'src/cpu/InstPBTrace.py')
-rw-r--r--src/cpu/InstPBTrace.py37
1 files changed, 37 insertions, 0 deletions
diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
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+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from InstTracer import InstTracer
+
+class InstPBTrace(InstTracer):
+ type = 'InstPBTrace'
+ cxx_class = 'Trace::InstPBTrace'
+ cxx_header = 'cpu/inst_pb_trace.hh'
+ file_name = Param.String("Instruction trace output file")