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authorEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es>2014-09-01 16:55:30 -0500
committerEmilio Castillo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E) <castilloe@unican.es>2014-09-01 16:55:30 -0500
commit01f792a3675983411ff77b54cbee7ffee2a3d5d5 (patch)
tree0f1d219ac9ff1d10b865d856d640884e2b177f13 /src/cpu/IntrControl.py
parent5efbb4442a0e8c653539e263bf87c48849280e23 (diff)
downloadgem5-01f792a3675983411ff77b54cbee7ffee2a3d5d5.tar.xz
ruby: Fixes clock domains in configuration files
This patch fixes scripts related to ruby by adding the ruby clock domain. Now the L1 controllers and the Sequencer shares the cpu clock domain, while the rest of the components use the ruby clock domain. Before this patch, running simulations with the cpu clock set at 2GHz or 1GHz will output the same time results and could distort power measurements. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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