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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-11-23 06:11:50 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-11-23 06:11:50 -0500 |
| commit | 40d434d5516affffe9ded9365e0d2da060aa7c78 (patch) | |
| tree | 095a480b2f025a4e113d09b693a6cb3c7ccf2040 /src/cpu/IntrControl.py | |
| parent | 3cd349f44305d6ca9496f7f626f0f4f939bd84ad (diff) | |
| download | gem5-40d434d5516affffe9ded9365e0d2da060aa7c78.tar.xz | |
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Diffstat (limited to 'src/cpu/IntrControl.py')
0 files changed, 0 insertions, 0 deletions