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authorGabe Black <gblack@eecs.umich.edu>2009-07-19 23:54:56 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-19 23:54:56 -0700
commit3e8e813218e7779a41bc12caae33db5e239506c9 (patch)
tree289f443de0f36590952706257e633132573b1493 /src/cpu/NativeTrace.py
parenta3a795769a2590451731f683ba11110f4035ab6b (diff)
downloadgem5-3e8e813218e7779a41bc12caae33db5e239506c9.tar.xz
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
Diffstat (limited to 'src/cpu/NativeTrace.py')
-rw-r--r--src/cpu/NativeTrace.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py
index f410b5473..7fd240543 100644
--- a/src/cpu/NativeTrace.py
+++ b/src/cpu/NativeTrace.py
@@ -31,5 +31,6 @@ from m5.params import *
from InstTracer import InstTracer
class NativeTrace(InstTracer):
+ abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'