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authorAndreas Hansson <andreas.hansson@arm.com>2013-09-04 13:22:57 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-09-04 13:22:57 -0400
commit19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch)
tree589541b322580a54e539e24932d3b4bba05801db /src/cpu/SConscript
parentea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff)
downloadgem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/cpu/SConscript')
-rw-r--r--src/cpu/SConscript4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index c52dbc53b..999de1e49 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -30,7 +30,9 @@
Import('*')
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
+ SimObject('IntrControl.py')
+ Source('intr_control_noisa.cc')
Return()
#################################################################