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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | f41df0ee08467711c613faadf9879052ab7196ed (patch) | |
| tree | b5ad5be9cecdec14d6f646e099edf9efcc8b38b0 /src/cpu/SConscript | |
| parent | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (diff) | |
| download | gem5-f41df0ee08467711c613faadf9879052ab7196ed.tar.xz | |
inorder-o3: allow both to compile together
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
Diffstat (limited to 'src/cpu/SConscript')
| -rw-r--r-- | src/cpu/SConscript | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 854db9f12..b14d606b7 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -128,6 +128,13 @@ Source('simple_thread.cc') Source('thread_context.cc') Source('thread_state.cc') +if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']: + Source('btb.cc') + Source('tournament_pred.cc') + Source('2bit_local_pred.cc') + Source('ras.cc') + TraceFlag('FreeList') + if env['FULL_SYSTEM']: SimObject('IntrControl.py') |