diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-29 13:25:14 -0700 |
---|---|---|
committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-29 13:25:14 -0700 |
commit | 08474ccf68e14f59b4517c6024a9bc6ecbd4a1d5 (patch) | |
tree | 5c1dc885b4fd33fc48d91a9ce489e24c88c9f3c2 /src/cpu/SConscript | |
parent | 4a7d0c4b79450e05b87da4cfc48c2361758127c1 (diff) | |
parent | 362ff1bcebd78c0c247e435eac657c8a1134b1fb (diff) | |
download | gem5-08474ccf68e14f59b4517c6024a9bc6ecbd4a1d5.tar.xz |
Merge Gabe's changes from head.
--HG--
extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
Diffstat (limited to 'src/cpu/SConscript')
-rw-r--r-- | src/cpu/SConscript | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index adf47fa4d..b686c0d95 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -105,12 +105,15 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] SimObject('BaseCPU.py') SimObject('FuncUnit.py') +SimObject('ExeTracer.py') +SimObject('IntelTrace.py') Source('activity.cc') Source('base.cc') Source('cpuevent.cc') Source('exetrace.cc') Source('func_unit.cc') +Source('inteltrace.cc') Source('pc_event.cc') Source('quiesce_event.cc') Source('static_inst.cc') @@ -123,6 +126,14 @@ if env['FULL_SYSTEM']: Source('intr_control.cc') Source('profile.cc') + if env['TARGET_ISA'] == 'sparc': + SimObject('LegionTrace.py') + Source('legiontrace.cc') + +if env['TARGET_ISA'] == 'x86': + SimObject('NativeTrace.py') + Source('nativetrace.cc') + if env['USE_CHECKER']: Source('checker/cpu.cc') checker_supports = False |