cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

     Benchmark     |   Stat host_seconds (s)
    ---------------+--------v--------v--------
     (on ARM, opt) | simple | o3     | minor
                   | timing | timing | timing
    ---------------+--------+--------+--------
    10.linux-boot  |   169  |  1883  |  1075
    10.mcf         |   117  |   967  |   491
    20.parser      |   668  |  6315  |  3146
    30.eon         |   542  |  3413  |  2414
    40.perlbmk     |  2339  | 20905  | 11532
    50.vortex      |   122  |  1094  |   588
    60.bzip2       |  2045  | 18061  |  9662
    70.twolf       |   207  |  2736  |  1036

1 files changed, 2 insertions, 0 deletions

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index ca9c6a791..1ea92114a 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -106,6 +106,7 @@ SimObject('ExeTracer.py')
 SimObject('IntelTrace.py')
 SimObject('IntrControl.py')
 SimObject('NativeTrace.py')
+SimObject('TimingExpr.py')
 
 Source('activity.cc')
 Source('base.cc')
@@ -123,6 +124,7 @@ Source('static_inst.cc')
 Source('simple_thread.cc')
 Source('thread_context.cc')
 Source('thread_state.cc')
+Source('timing_expr.cc')
 
 if env['TARGET_ISA'] == 'sparc':
     SimObject('LegionTrace.py')