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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:17 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:17 -0500 |
| commit | 0bd986015b2de741dc741f10e5afeaf5d8890ba1 (patch) | |
| tree | b264b3fd434124d7b04eb4a6b337cb38e8ccb305 /src/cpu/SConscript | |
| parent | 6c4a23c1c637d77f60df9516d0f36c71d12a2298 (diff) | |
| download | gem5-0bd986015b2de741dc741f10e5afeaf5d8890ba1.tar.xz | |
cpu: Put all CPU instruction tracers in a single file
Diffstat (limited to 'src/cpu/SConscript')
| -rw-r--r-- | src/cpu/SConscript | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 0f5d53b37..88ea535b7 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -38,11 +38,9 @@ if env['TARGET_ISA'] == 'null': SimObject('CheckerCPU.py') SimObject('BaseCPU.py') +SimObject('CPUTracers.py') SimObject('FuncUnit.py') -SimObject('ExeTracer.py') -SimObject('IntelTrace.py') SimObject('IntrControl.py') -SimObject('NativeTrace.py') SimObject('TimingExpr.py') Source('activity.cc') |