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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-09-30 00:28:33 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-09-30 00:28:33 -0700 |
| commit | 51f7a6666027870c24432dcaa56cfc1b4741fdc6 (patch) | |
| tree | 6dd74cdab55616bae7c974bc6c4fc39e60c9808a /src/cpu/SConscript | |
| parent | 35e20c7470a16cbc1187553375269800b980eb78 (diff) | |
| download | gem5-51f7a6666027870c24432dcaa56cfc1b4741fdc6.tar.xz | |
SE/FS: Build the devices in SE mode.
Diffstat (limited to 'src/cpu/SConscript')
| -rw-r--r-- | src/cpu/SConscript | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript index a1074cb8b..370b83909 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -109,6 +109,7 @@ SimObject('BaseCPU.py') SimObject('FuncUnit.py') SimObject('ExeTracer.py') SimObject('IntelTrace.py') +SimObject('IntrControl.py') SimObject('NativeTrace.py') Source('activity.cc') @@ -118,6 +119,7 @@ Source('decode.cc') Source('exetrace.cc') Source('func_unit.cc') Source('inteltrace.cc') +Source('intr_control.cc') Source('nativetrace.cc') Source('pc_event.cc') Source('quiesce_event.cc') @@ -127,9 +129,6 @@ Source('thread_context.cc') Source('thread_state.cc') if env['FULL_SYSTEM']: - SimObject('IntrControl.py') - - Source('intr_control.cc') Source('profile.cc') if env['TARGET_ISA'] == 'sparc': |