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| author | Ian Jiang <ianjiang.ict@gmail.com> | 2019-11-14 16:41:25 +0800 |
|---|---|---|
| committer | Ian Jiang <ianjiang.ict@gmail.com> | 2019-11-26 03:38:22 +0000 |
| commit | 390f7b917757887674ab441979f36bffeedb646a (patch) | |
| tree | b9c6e3a4d7201bd08b871cbf247fa53576cbf9c8 /src/cpu/SConscript | |
| parent | 57e951f6eae1de88988a9b13035c07985a0bcd73 (diff) | |
| download | gem5-390f7b917757887674ab441979f36bffeedb646a.tar.xz | |
arch-riscv: Fix disassembling for fence and fence.i
The original Gem5 does not give correct disassembly for instruction fence
and fence.i. This patch fixes the problem by adding two bitfields PRED and
SUCC and a new format FenceOp and a template FenceExecute, in which
operands are generated based on PRED and SUCC in the disassembling
function.
Change-Id: I78dbf125fef86ce40785c498a318ffb1569da46c
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22569
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/cpu/SConscript')
0 files changed, 0 insertions, 0 deletions