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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
| commit | 608641e23c7f2288810c3f23a1a63790b664f2ab (patch) | |
| tree | 0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/cpu/StaticInstFlags.py | |
| parent | 6e354e82d9395b20f5f148cd545d0666b626e8ac (diff) | |
| download | gem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz | |
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Diffstat (limited to 'src/cpu/StaticInstFlags.py')
| -rw-r--r-- | src/cpu/StaticInstFlags.py | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py index ef29726fc..3b00e5df8 100644 --- a/src/cpu/StaticInstFlags.py +++ b/src/cpu/StaticInstFlags.py @@ -55,8 +55,8 @@ class StaticInstFlags(Enum): vals = [ 'IsNop', # Is a no-op (no effect at all). - 'IsInteger', # References integer regs. - 'IsFloating', # References FP regs. + 'IsInteger', # References scalar integer regs. + 'IsFloating', # References scalar FP regs. 'IsCC', # References CC regs. 'IsMemRef', # References memory (load, store, or prefetch) @@ -108,5 +108,6 @@ class StaticInstFlags(Enum): 'IsMicroBranch', # This microop branches within the microcode for # a macroop 'IsDspOp', - 'IsSquashAfter' # Squash all uncommitted state after executed + 'IsSquashAfter', # Squash all uncommitted state after executed + 'IsVector', # References vector register. ] |