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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-11 12:57:36 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 08:28:51 +0000 |
| commit | ef984784289f8bd4ddedcc4a6ead2c45704cc35b (patch) | |
| tree | 5aa675bf8edb27f8895deb8f05e1de8a66233107 /src/cpu/TimingExpr.py | |
| parent | 058e2cec7c56bf0549efff1df5974799c41cd1be (diff) | |
| download | gem5-ef984784289f8bd4ddedcc4a6ead2c45704cc35b.tar.xz | |
dev-arm: Fix GICv2 cpu interrupt enable flag
Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register
as if writing any non-zero value to the register will enable IRQ
signaling to the CPU. Instead, only the 2 least significant bits
control group0/group1 enablement. This patch is renaming GICC_CTRL
underlying data buffer from cpuEnabled to cpuControl and it is making it
an array of uint32_t instead of bool. cpuEnabled now becomes a method
and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set.
Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/TimingExpr.py')
0 files changed, 0 insertions, 0 deletions