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author | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-08 18:18:28 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2007-01-08 18:18:28 -0500 |
commit | 032ea9b2db870ad9b2a039f8c4020e38f5dd7f62 (patch) | |
tree | 633ac09003332159db2e948c68523a2b0bccfdab /src/cpu/activity.cc | |
parent | b45219e7ae747619571dbb7245dd3409b96c473f (diff) | |
download | gem5-032ea9b2db870ad9b2a039f8c4020e38f5dd7f62.tar.xz |
the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
fill in how we do interrupts on sparc a little bit.
1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
2) fill in getInterrupts() a little bit.
also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
1) update formatting
2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.
--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
Diffstat (limited to 'src/cpu/activity.cc')
0 files changed, 0 insertions, 0 deletions