cpu: Remove CpuPort and use MasterPort in the CPU classes

This patch changes the port in the CPU classes to use MasterPort
instead of the derived CpuPort. The functions of the CpuPort are now
distributed across the relevant subclasses. The port accessor
functions (getInstPort and getDataPort) now return a MasterPort
instead of a CpuPort. This simplifies creating derivative CPUs that do
not use the CpuPort.

1 files changed, 1 insertions, 22 deletions

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 36caea79a..de0f8b23b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -312,7 +312,7 @@ BaseCPU::getMasterPort(const string &if_name, PortID idx)
     // Get the right port based on name. This applies to all the
     // subclasses of the base CPU and relies on their implementation
     // of getDataPort and getInstPort. In all cases there methods
-    // return a CpuPort pointer.
+    // return a MasterPort pointer.
     if (if_name == "dcache_port")
         return getDataPort();
     else if (if_name == "icache_port")
@@ -585,24 +585,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
         functionEntryTick = curTick();
     }
 }
-
-bool
-BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
-{
-    panic("BaseCPU doesn't expect recvTiming!\n");
-    return true;
-}
-
-void
-BaseCPU::CpuPort::recvRetry()
-{
-    panic("BaseCPU doesn't expect recvRetry!\n");
-}
-
-void
-BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
-{
-    // No internal storage to update (in the general case). A CPU with
-    // internal storage, e.g. an LSQ that should be part of the
-    // coherent memory has to check against stored data.
-}