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authorSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) <stever@gmail.com>2013-11-25 11:21:00 -0600
committerSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) <stever@gmail.com>2013-11-25 11:21:00 -0600
commitde366a16f11b7e27a5b5e064a2a773052568428e (patch)
tree9bed0ebc9801c118e0f17702a979a659a59a67df /src/cpu/base.cc
parent8a53da22c2f07aed924a45ab296f7468d842d7f6 (diff)
downloadgem5-de366a16f11b7e27a5b5e064a2a773052568428e.tar.xz
sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
Diffstat (limited to 'src/cpu/base.cc')
-rw-r--r--src/cpu/base.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 25fe9bf97..3078472fd 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -13,6 +13,8 @@
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * Copyright (c) 2013 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -569,7 +571,7 @@ void
BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
{
const Tick now(comInstEventQueue[tid]->getCurTick());
- Event *event(new SimLoopExitEvent(cause, 0));
+ Event *event(new LocalSimLoopExitEvent(cause, 0));
comInstEventQueue[tid]->schedule(event, now + insts);
}
@@ -578,7 +580,7 @@ void
BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
{
const Tick now(comLoadEventQueue[tid]->getCurTick());
- Event *event(new SimLoopExitEvent(cause, 0));
+ Event *event(new LocalSimLoopExitEvent(cause, 0));
comLoadEventQueue[tid]->schedule(event, now + loads);
}